1. Technical Field
The present invention relates to a voltage supply for bit lines, and more particularly, to a bit line voltage supply circuit in a volatile semiconductor memory device and a voltage supplying method therefor.
2. Discussion of Related Art
To achieve higher performance in electronic systems such as personal computers or electronic communication devices, volatile semiconductor memory devices such as static random access memories (SRAM) are more highly integrated with higher response speed. Since semiconductor memory devices installed in battery operated systems such as hand held telephones or notebook computers benefit from low power consumption characteristics, semiconductor device manufacturers are reducing operating current and standby current to provide a mobile-oriented low power solution.
FIG. 1 is a circuit diagram of a memory cell of a conventional static random access memory. With reference to FIG. 1, a memory cell of a static random access memory (SRAM) is typically comprised of six CMOS transistors, including first and second load transistors P1 and P2, first and second driver transistors N1 and N2, and first and second access (pass) transistors N3 and N4. According to a tendency toward higher integration of semiconductor memory devices, when the cell density of an SRAM is further increased to a limit of resolution of a photolithography process, the six CMOS transistors may be situated on different layers. One memory cell MC functions as a single memory unit capable of storing one bit of data (0 or 1). A supply voltage Vdd is applied to source terminals of the first and second load transistors P1 and P2. Drain (or source) terminals of the first and second pass transistors N3 and N4 are connected to a bit line pair comprised of a bit line BL and a complementary bit line BLb, respectively.
FIG. 2 is a circuit diagram showing a core cell array of a conventional static random access memory having a plurality of memory cells as shown in FIG. 1. As in FIG. 2, a plurality of memory cells MC1 to MCn and a precharge and equalization section 100 are connected to a bit line pair BL and BLb. First, second, third and fourth column pass gates MP1, MP2, MN1 and MN2 are coupled with the bit line pair BL and BLb to connect the bit line pair BL and BLb with read and write section data line pairs RSDL, RSDLb, WSDL and WSDLb. More specifically, the first and second column pass gates MP1 and MP2, typically comprised of pMOS transistors, transfer cell data from the bit line pair BL and BLb to the read section data line pair RSDL and RSDLb, respectively, in response to a complementary column select signal Yb. The third and fourth column pass gates MN1 and MN2, typically comprised of nMOS transistors, transfer write data provided from a write driver connected to the write section data line pair WSDL and WSDLb, to the bit line pair BL and BLb, respectively, in response to a column select signal Y.
Because a precharge and equalization control signal YEQ applied to the precharge and equalization section 100 becomes a logic low during a standby mode, the bit line pair BL and BLb is precharged to the supply voltage Vdd through activation of first through third precharge transistors PP1 to PP3, which are typically pMOS transistors. Accordingly, leakage current flowing through the first and second pass transistors N3 and N4 of a memory cell MC occurs during a standby mode.
That is, when the semiconductor memory device operates in a standby mode, the bit line pair BL and BLb is precharged to a supply voltage Vdd and a leakage current flows into the first and second pass transistors N3 and N4 from the bit line pair BL and BLb to ground through two paths A1 and A2. Thus, two paths A1 and A2 of leakage current are formed between the bit line pair BL and BLb and ground through the first and second pass transistors N3 and N4, respectively.
Furthermore, source-drain channels of the first and second load transistors P1 and P2 provide additional paths for leakage current. Because the supply voltage Vdd is applied to the source terminals of the first and second load transistors P1 and P2 to maintain data storage, a memory cell power leakage current also flows through the first and second load transistors P1 and P2.
Conventional methods to reduce leakage current flowing through the first and second load transistors P1 and P2, include applying a voltage lower than the level of the supply voltage Vdd as the memory cell power voltage during a standby mode, and applying the supply voltage Vdd as the memory cell power voltage during an operational mode.
However, the conventional methods for reducing leakage current reduce only a standby current flowing through the first and second load transistors P1 and P2 of a memory cell MC. However, the conventional methods do not reduce leakage current flowing from a bit line pair BL and BLb to ground through the first and second pass transistors N3 and N4. As a result, there is a limitation on the reduction of standby current in a standby mode by means of the conventional methods.
Accordingly, what is desired is a circuit capable of reducing leakage current flowing from bit lines to a memory cell without deteriorating the performance of a semiconductor memory device such as employed in battery operated systems.